FIGS. 9A and 9B are a plan view and a cross sectional view of an NPN type bipolar transistor (Bi-Tr) as a portion of a conventional semiconductor device, e.g., Bi-CMOS, respectively. This Bi-Tr is manufactured as follows. Namely, an N.sup.+ type buried layer 2 is formed on a P-type Si substrate 1 and an N-type collector region 3 is grown thereon. A P-type impurity (B or BF.sub.2, etc.) is ion-implanted into a region where the base is to be formed of the collector region 3. Thereafter, using a resist mark, an N-type impurity (e.g., As) is ion-implanted only into a region where the emitter is to be formed in the region where the base is to be formed. Heat treatment is then conducted. As a result, a P-type base region 4 is formed within the N-type collector region 3, and an N-type emitter region 5 is formed within the P-type base region 4. Thus, a Bi-Tr is provided.
There are instances where a reverse bias may be applied to the junction portion between the emitter region 5 and the base region 4 of the Bi-Tr. Application of such a reverse bias leads to the difficulty that the emitter-base junction breakdown voltage is lowered and the current gain h.sub.FE is also lowered, resulting in considerably deteriorated device characteristics.